Real-time Simulation of Dynamic Vehicle Models using a High-performance Reconfigurable Platform

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Karkee, Manoj
Sun, Song
Steward, Brian
Kelkar, Atul
Zambreno, Joseph
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Zambreno, Joseph
Steward, Brian
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Agricultural and Biosystems Engineering

Since 1905, the Department of Agricultural Engineering, now the Department of Agricultural and Biosystems Engineering (ABE), has been a leader in providing engineering solutions to agricultural problems in the United States and the world. The department’s original mission was to mechanize agriculture. That mission has evolved to encompass a global view of the entire food production system–the wise management of natural resources in the production, processing, storage, handling, and use of food fiber and other biological products.

In 1905 Agricultural Engineering was recognized as a subdivision of the Department of Agronomy, and in 1907 it was recognized as a unique department. It was renamed the Department of Agricultural and Biosystems Engineering in 1990. The department merged with the Department of Industrial Education and Technology in 2004.

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  • Department of Agricultural Engineering (1907–1990)

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Agricultural and Biosystems Engineering

A purely software-based approach for Real-Time Simulation (RTS) may have difficulties in meeting real-time constraints for complex physical model simulations. In this paper, we present a methodology for the design and im-plementationofRTS algorithms,basedontheuseof Field-ProgrammableGateArray(FPGA) technologytoimprove the response time of these models. Our methodology utilizes traditional hardware/software co-design approaches to generate a heterogeneous architecture for an FPGA-based simulator. The hardware design was optimized such that it efficiently utilizes the parallel nature of FPGAs and pipelines the independent operations. Further enhancement is obtained through the use of custom accelerators for common non-linear functions. Since the systems we examined had relatively low response time requirements, our approach greatly simplifies the software components by porting the computationally complexregionsto hardware.We illustratethe partitioningofa hardware-based simulator design across dual FPGAs, initiateRTS usinga system input froma Hardware-in-the-Loop (HIL) framework, and use these simulation results from our FPGA-based platform to perform response analysis. The total simulation time, which includes the time required to receive the system input over a socket (without HIL), software initialization, hardware computation, and transferof simulation results backovera socket, showsa speedup of 2× as compared to a simi-lar setup with no hardware acceleration. The correctness of the simulation output from the hardware has also been validated with the simulated results from the software-only design.


This article was published in Procedia Computer Science 9 (2012): 338–347, doi:10.1016/j.procs.2012.04.036 under a Creative Commons license (CC BY-NC-ND 3.0).

Sun Jan 01 00:00:00 UTC 2012