A new architecture for poly-silicon fuse circuits

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2000
Authors
Ismail, Ahmed Ezzat
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Geiger, Randall L.
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Abstract
Trimming techniques are widely used in the microelectronics industry. They are used in field programmable arrays, memory repair, calibration, and as a general memory element in Read Only Memories (ROMs). Various trimming techniques have developed to suit varying requirements. Most, however, require special processing steps, expensive trimming equipment, or large amounts of silicon area. In this thesis, I have focused on practically providing the designer with a large number of electrically trimmable poly-silicon fuses that are compatible with low-cost, high-volume semiconductor processes. Since electrically blowing poly-silicon fuses requires a large current to drive the fuse into thermal runaway, existing approaches use a large transistor for each fuse. This makes the use of many fuses on one chip economically unviable. With the former approach, the required area is linearly dependent upon the number of fuses, whereas an optimal matrix approach has an area that approximately depends on the square root of the number of fuses. This quadratic reduction in area will make it practical to include a large number of trim elements in many circuits. This thesis presents a new architecture, in which the fuses are arranged in an array structure using 1024 fuses (32 x 32). There is a total of 64 of the large transistors, 32 for the rows and 32 for the columns. This drives down the average number of large transistors per fuse from 1 to 0.0625 (1024/64), resulting in a 16:1 area savings.
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