On-Chip Adaptive Circuits for Fast Media Processing
dc.contributor.author | Sangireddy, Rama | |
dc.contributor.author | Somani, Arun | |
dc.contributor.author | Somani, Arun | |
dc.contributor.department | Electrical and Computer Engineering | |
dc.date | 2021-02-10T16:33:13.000 | |
dc.date.accessioned | 2021-02-25T17:18:46Z | |
dc.date.available | 2021-02-25T17:18:46Z | |
dc.date.copyright | Sun Jan 01 00:00:00 UTC 2006 | |
dc.date.issued | 2006-09-01 | |
dc.description.abstract | <p>Applications, depending on their nature, demand either higher computing capacity, larger data-storage capacity, or both. Hence, providing on-chip memory and computing resources that are fixed in nature is expensive and does not enable an efficient utilization of on-chip silicon real estate. In this brief, we design the circuit of an adaptive register file computing (ARC) unit, a novel on-chip dual-role circuit with a minimal area overhead of 0.233 mm 2 at 0.18-mu technology. It supplements the conventional register bank to provide larger register storage capacity or acts as a specialized computing unit to provide higher on-chip computing capacity, depending on the requirement of a specific application. The brief discusses the circuit-level details for the implementation of the dual-role ARC unit, its integration in a wide-issue processor pipeline, and the corresponding performance enhancement in various multimedia applications.</p> | |
dc.description.comments | <p>This is a manuscript of an article published as Sangireddy, Rama, and Arun K. Somani. "On-chip adaptive circuits for fast media processing." <em>IEEE Transactions on Circuits and Systems II: Express Briefs</em> 53, no. 9 (2006): 946-950. DOI: <a href="https://doi.org/10.1109/TCSII.2006.880336" target="_blank">10.1109/TCSII.2006.880336</a>. Posted with permission.</p> | |
dc.format.mimetype | application/pdf | |
dc.identifier | archive/lib.dr.iastate.edu/ece_pubs/295/ | |
dc.identifier.articleid | 1295 | |
dc.identifier.contextkey | 21568102 | |
dc.identifier.s3bucket | isulib-bepress-aws-west | |
dc.identifier.submissionpath | ece_pubs/295 | |
dc.identifier.uri | https://dr.lib.iastate.edu/handle/20.500.12876/94002 | |
dc.language.iso | en | |
dc.source.bitstream | archive/lib.dr.iastate.edu/ece_pubs/295/2006_SomaniArun_OnChip.pdf|||Fri Jan 14 23:15:14 UTC 2022 | |
dc.source.uri | 10.1109/TCSII.2006.880336 | |
dc.subject.disciplines | Digital Circuits | |
dc.subject.disciplines | Hardware Systems | |
dc.subject.disciplines | Signal Processing | |
dc.subject.keywords | Multimedia | |
dc.subject.keywords | reconfigurable computing | |
dc.subject.keywords | register file | |
dc.title | On-Chip Adaptive Circuits for Fast Media Processing | |
dc.type | article | |
dc.type.genre | article | |
dspace.entity.type | Publication | |
relation.isAuthorOfPublication | edede50a-4e31-44f3-a7c7-a06dc8db42c2 | |
relation.isOrgUnitOfPublication | a75a044c-d11e-44cd-af4f-dab1d83339ff |
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