An asynchronous data recovery/retransmission technique with foreground DLL calibration
Date
2000
Authors
Nagavarapu, Sudha
Major Professor
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Geiger, Randall L.
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Abstract
Devices connected in a Local Area Network (LAN) communicate with each other by means of serial transmission of bits. Serial data is transmitted without an accompanying clock to reduce bandwidth requirements and pin-out count. Synchronization is performed at the receiving end. The presence of timing jitter and noise in the incoming data makes Data Recovery on such a system a non-trivial problem. Traditional Data Recovery approaches have focused on recovering a bit clock from the incoming data and using clock transitions to read the data. In this thesis, a new technique for asynchronous data recovery based upon using a delay line in the incoming data path is introduced. The proposed data recovery system is well suited for tight tolerance channels and coding systems supporting standards that limit the maximum number of consecutive 0's and 1's in a data stream.
It samples incoming data in the delay line on transitions of the data itself and has a reduced sensitivity to jitter when compared to standard PLL-based data recovery systems. In contrast to PLL-based systems that often lose a large number of bits during acquisition (locking), the proposed technique actually recovers all data in the channel for a fixed interval prior to the first data transition. Precise delays in the delay line are generated by a system clock driven DLL that can enter the sleep mode after calibration to conserve power and minimize switching noise injection into the bulk. The asynchronous technique recovers the incoming data without recovering a clock signal. When used in a transceiver, retimed data with a very low jitter that is essentially independent of the jitter on the incoming data stream is retransmitted. The system has inherent latency due to its asynchronous nature. It hus has memory that can be designed to allow for elasticity.
This is an advantage in systems with finite clock tolerances. The preliminary architecture for the asynchronous scheme is presented and experimental results are presented to prove the efficacy of the approach.
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thesis