Performance improvement techniques with Built-in Self-test based calibration ability for analog and mix-signal circuits

Abstract

In this dissertation, several methods for improving the performance of analog and mixed-signal system are presented. The proposed techniques take the advantage of the built-in self-testing circuit based calibration capabilities to not only improve the performance but also relax the design efforts for designers and the costs for production testing, which are the most desired in the production flow for analog and mix-signal systems. It is shown that by applying the proposed techniques, the traditional design of the analog and mixed-signal circuits can be improved to achieve better performance but not introduce power and area overhead compared with the traditional methods for performance enhancement.

Operational amplifiers (op amps) are one of the most fundamental and most widely used building blocks for analog and mixed-signal circuits and systems. As the transistors’ feature size scales down in the deep sub-micron process, the short channel effects, high leakage current ,and reduced supply voltages make the design of op amps more challenging. In this chapter, we present a new topology of folded-cascode amplifier with the improvement of DC gain, slew rate, power efficiency, and current utilization efficiency (CUE).

SEIR(Stimulus error identification and removal) based ADC BIST can significantly reduce the test signal linearity requirement thus this method is a cost-effective BIST solution for ADC linearity testing. However, a high constant level shift is required during testing and the stimulus signal needs to cover the whole ADC input range or even over-range. A new SEIR-based BIST for ADC linearity testing is developed. The new BIST consists of a high constant level shift generator and a ramp generator with level spreading DAC. The proposed BIST circuit can provide true rail-to-rail performance that can test the whole ADC input range and the constancy of level shift can achieve 15ppm with CLS (Correlated Level Shifting) technique. The BIST has been fabricated in TI 65nm technology and integrated with 12-bit ADC. The measurement results show that it can test a 14-bit ADC accurately within 1 LSB estimation error.

A calibration technique for SAR analog-to-digital converters is proposed in this paper which is ready to be integrated on chip. This technique is based on the integral nonlinearity (INL) test and utilizes one redundant bit and extra two quantization bits to improve the calibration accuracy. In the calibration mode, mismatch errors are saved as higher-bit level INL information and then translated to calibration codes. During the conversion, higher-bit level outputs are adjusted and truncated to generate the required bits. Finally, 0.375LSB improvement of INL is observed by theoretical analysis and the effectiveness of this method is verified by simulations in which the maximum INL is reduced from 0.9LSB to 0.23LSB. And the measurement results show that the proposed calibration method could improve the linearity performance from 12bit to 14bit level.

A novel time skew calibration method for time-interleaved analog-to-digital converters(TI ADCs) is proposed. The method is based on linear approximation and does not require complex implementation in the digital domain. With only register and adders, the time skew detection can be accomplished with the output codes. The calibration method adopts successive approximation logic in the digital domain to drastically reduce the calibration iteration cycles. The new method processed in the digital domain can reduce the iterations to only two cycles for two-channel TI ADCs. The simulation results show the high performance and efficiency of the proposed methods.