Reducing integrated circuit test cost through improvements in multisite testing and built-in self-test

Abstract

<p>The semiconductor industry is continually growing, and integrated electronics are increasingly assimilating into our daily lives. As these electronics grow in complexity, the cost of testing them has become a significant challenge to the industry. Two methods that are utilized by test engineers to reduce test costs are parallelism and built-in self-test (BIST). Parallelism is implemented with multisite testing but suffers from site-to-site variations. BIST reduces the tester’s string requirements but faces challenges due to area limitations. In this thesis, two methods to identify site-to-site variations in multisite testing are developed, and an improved switch sizing for BIST solutions is presented.</p> <p>The two algorithms developed identify site-to-site variations in multisite testing by comparing each site’s distribution against an approximation of the parameter’s variation-free distribution. These algorithms produce scores that quantify how much site-to-site variation is present in each site’s data, a capability that traditional inferential statistical tests fail to provide. The two methods were compiled into a software package that was transferred to Texas Instruments.</p> <p>Further efforts were made to utilize the algorithm scores to identify root causes of site-to-site variations. The tester board was simulated using two different simulations methods, and various parameters were extracted. These parameters were correlated with scores from the two methods and the original volume probe data. Preliminary results were obtained that can serve as an initial step to developing a method that automatically identifies issues with test boards that cause site-to-site variations.</p> <p>Finally, an improved area allocation technique is presented that improves shift constancy for analog-to-digital converter BIST. The proposed sizing algorithm was developed after reviewing a previous analog-to-digital converter BIST design. By employing this sizing strategy, the shift constancy of the BIST is improved by a factor of two. Decreasing the voltage shift error allows the USER-SMILE algorithm (the testing method used by the BIST solution) to test higher resolution ADCs.</p>