An FPGA architecture for the recovery of WPA/WPA2 keys

dc.contributor.advisor Joseph Zambreno
dc.contributor.author Johnson, Tyler
dc.contributor.department Department of Electrical and Computer Engineering
dc.date 2018-08-11T09:48:08.000
dc.date.accessioned 2020-06-30T02:51:15Z
dc.date.available 2020-06-30T02:51:15Z
dc.date.copyright Wed Jan 01 00:00:00 UTC 2014
dc.date.embargo 2001-01-01
dc.date.issued 2014-01-01
dc.description.abstract <p>Wi-Fi protected access (WPA) has provided serious improvements over the now deprecated wired equivalent privacy protocol (WEP). WPA, however, still has some flaws that allow an attacker to obtain the passphrase. One of these flaws is exposed when the access point (AP) is operating in the WPA personal mode. This is the most common mode as it is the quickest and easiest to configure. It requires the attacker to capture the traffic from four-way handshake between the AP and client, and then provide enough compute time to reverse the passphrase. Attackers quickly noticed that by investing the compute time in advance, and storing their work, they could decrease the time-to-crack for an AP. This caused attackers to start compiling large lookup tables based on dictionaries of common passwords and common SSIDs. The attackers are required to compile a separate lookup table for each SSID, making this style of attack most feasible against APs with a common SSID and password.</p> <p>The work in this thesis will focus on creating an FPGA based architecture to accelerate the generation of the lookup table, given a dictionary of possible Pre-shared Keys and an SSID. The application of this work would be most useful for attacking one-off SSID's. This is because most common SSID's already have a generated lookup table that can be downloaded much faster than it could be generated, so this regeneration would be wasteful. The application will also provide a manner to check for a valid Pairwise Master Key during the table generation phase.</p>
dc.format.mimetype application/pdf
dc.identifier archive/lib.dr.iastate.edu/etd/13658/
dc.identifier.articleid 4665
dc.identifier.contextkey 5777346
dc.identifier.doi https://doi.org/10.31274/etd-180810-1194
dc.identifier.s3bucket isulib-bepress-aws-west
dc.identifier.submissionpath etd/13658
dc.identifier.uri https://dr.lib.iastate.edu/handle/20.500.12876/27845
dc.language.iso en
dc.source.bitstream archive/lib.dr.iastate.edu/etd/13658/Johnson_iastate_0097M_14058.pdf|||Fri Jan 14 19:57:53 UTC 2022
dc.subject.disciplines Computer Engineering
dc.subject.disciplines Computer Sciences
dc.subject.disciplines Databases and Information Systems
dc.subject.keywords FPGA
dc.subject.keywords High Performance Reconfigurable Computing
dc.subject.keywords Security
dc.subject.keywords WiFi
dc.title An FPGA architecture for the recovery of WPA/WPA2 keys
dc.type thesis en_US
dc.type.genre thesis en_US
dspace.entity.type Publication
relation.isOrgUnitOfPublication a75a044c-d11e-44cd-af4f-dab1d83339ff
thesis.degree.level thesis
thesis.degree.name Master of Science
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