State encoding for low power
Date
1996
Authors
Bhupathi, Lakshmikant
Major Professor
Advisor
Chao, Liang-Fang
Committee Member
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Abstract
In this thesis, methods are proposed to minimize power consumption in mutilevel logic implementations of FSMs during the state encoding step. Information theoretic measures are used to model the power consumption in the circuit. It is shown that the power measure can be reduced by introducing a skew in the probability of state bits. The states are partitioned into groups to introduce skew and then an area measure based maximum matching technique is applied to keep the area down. The use of non-minimal length encoding to further reduce power is investigated. The results indicate that non-minimal length encoding is good for power reduction in most cases. They also prove that entropy based power measures can be used to model power in multi-level logic circuits.
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Type
thesis