## A graphical method for determining the uniqueness of operating points in self-biasing circuits 2015-01-01
Liu, Shiya
Randall Geiger
##### Department
Electrical and Computer Engineering
##### Abstract

In self-biasing circuits, designers often use feedbacks to reduce the power-supply sensitivity and minimize the effects of process and temperature variations. Many self-stabilized circuits are used in SOC circuits even when the SOC has a small amount of AMS content. It is well-known that these self-stabilized circuits are vulnerable to not "starting-up" correctly so start-up circuits are often included to prevent the circuit from getting stuck in an undesired stable operating point. Determining the uniqueness of an operating point in a circuit is challenging since circuit simulators only give a single operating point rather than all operating points. Moreover, this problem is very closely related to the mathematical problem of finding all solutions to a set of nonlinear equations. Both the mathematical and computer science communities recognize this as an open problem with no solution in sight. In circuits with multiple operating points, when a circuit simulator always gives the desired operating point throughout the design and verification process, there is little evidence that one or more undesired operating points even exist. In the semiconductor industry, designers use experience and intuition to identify start-up problems. Some self-stabilized circuits designed by trusted engineers unpredictably get stuck in an undesirable operating point. Engineers often attempt to verify start-up effectiveness with transient simulations. This approach is heuristic and time consuming. Moreover, multiple operating points may still exist in circuits.

All circuits we have studied with known need for start-up circuits have a positive feedback loop (PFL) as part of the self-stabilization process. As a result, we made a conjecture that, "A circuit is vulnerable to the multiple operating points problem only if the circuit has one or more Positive Feedback Loops." A graphical method for identifying positive feedback loops in analog circuits is presented for the purpose of identifying the stable equilibrium points. Firstly, since our method is based on graphical concepts, some key terminologies from graph theory will be reviewed. Secondly, Graphical models for key analog components are developed and then hierarchically used to obtain a graphical representation of an analog circuit. Thirdly, the concept of determining positive feedback loops from the small-signal resistive Directed, Weighted, Multi-Graph (DWM Graph) of a circuit will be addressed. The three-step process will be used to determine the positive feedback loops. Lastly, a method for breaking positive feedback loop and how to apply the homotopy method to create a return map for the positive feedback loop is introduced. By breaking the positive feedback loop in the circuit and applying break-loop homotopy method, it can determine the uniqueness of operating points in self-biasing circuits.

Sample-and-hold circuit is wildly used in mixed-signal circuits such as data converters, filters etc. Thermal noise is often a design limitation in mixed-signal designs. Many literatures and analog textbooks state that the thermal noise voltage sampled on a capacitor is where k is Boltzmann constant, T is temperature and C is capacitance .

From the expression of thermal noise voltage, we can find that thermal noise is highly related to the capacitor values and independent of resistors. The only way to reduce thermal noise voltage is to increase the capacitance. However, a large capacitor increases the settling time and reduce sampling rate. Meanwhile, layout area and power dissipation will be increased. There is a tradeoff between settling time and accuracy. No literatures introduce a method for reducing thermal noise without increasing capacitance. Reducing noise on a sampling capacitor below may give designers opportunities for improving system performance. A method for reducing thermal noise voltage on a sampling capacitor dramatically below is introduced.

In high resolution SAR ADC design, many papers state that the minimum capacitance of capacitor DAC is determined by the thermal noise limitation. This thermal noise limitation is kT/C where k is Boltzmann constant, T is temperature and C is the total capacitance of capacitor DAC. Moreover, they assume this is the input-referred noise for the whole ADC. However, this calculation ignores the noise from charge-redistribution mode completely. Meanwhile, no literatures introduce any method about numerical calculation of thermal noise from charge-redistribution mode of capacitor DAC of SAR ADC. A numerical calculation of thermal noise from charge-redistribution mode of capacitor DAC of SAR ADC is introduced.