Design techniques and implementations of high-speed analog communication circuits: two analog-to-digital converters and a 3.125Gb/s receiver
Low-cost and high performance analog building blocks are essentials to the realization of today's high-speed networking and communications systems. Two such building blocks are analog-to-digital converters (ADCs) and multi-gigabit per second transceivers. This thesis addresses two different ADC architectures and a 3.125Gb/s receiver Architecture;The first ADC architecture is a 10-bit, 100MS/s pipeline ADC. Techniques that enhance the gain-bandwidth of the operational amplifier, a key building block in analog-to-digital converters, as well as to increase its do gain are presented. Layout techniques to reduce the effect of parasitics on the performance of the ADC are also discussed. Since any ADC will have inherent errors in it, two calibration techniques that reduce the effect of these errors on the performance of the ADC are also presented.;For the second ADC, a new architecture is proposed that is capable of achieving higher performance than many current ADC architectures. The new architecture is based on a voltage controlled oscillator and a frequency detector. One reason for the high performance of the new ADC is the novel architecture of the frequency detector. This thesis includes detailed analysis as well as examples to illustrate the operation of the frequency detector.;Designing high-speed CMOS transceivers is a challenging process, especially, when using digital CMOS process that exhibits poor analog performance. Circuit implementation and design techniques that are used to design and enhance the performance of the receiver block of a 3.125Gb/s transceiver in a 0.18u digital CMOS process are presented and fully explained in this thesis. Silicon results have shown that these techniques have resulted in outstanding and very robust receiver performance under different operating conditions.