CMOS circuits for high speed serial data communication

Date
1997
Authors
Xi, Xiaoyu
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Abstract

The serial data link has been dominant in network connections, such as Ethernet, FDDI or ATM, and will find even wider application in the future. This work focuses on the implementation of some basic building blocks for very high speed serial data communication using CMOS technology. At the transmitter end, a novel parallel-to-serial converter is presented, whose core is a 5 by 4 register matrix which combines the selection and shift schemes for conversion. Using this architecture, a pipelined data loading is applied to multiple data paths running at a sub-multiple of the data rate. This significantly reduces the dynamic power dissipation and eases the system design. The special clock strategy to drive the converter is investigated in this work. SPICE simulations and a chip layout of this method are presented.;At the receiver end, a clock recovery circuit based on a charge pump phase locked loop is proposed. The VCO has an internal feedback loop to adjust the duty cycle at different frequency. A simple conventional phase detector with a limited output swing is used to achieve the high working frequency. A modified symmetrical charge pump circuit improves linearity of the output current versus the input UP and DOWN signal. Some characteristics such as impulse capture range and lock range are estimated from the simulations. All the designs assume 0.5um single-poly triple-metal CMOS technology. This work presents an analysis to the system as well as individual parts and explores the possibility of CMOS solutions for gigabit data communication. It could be used or adopted in future designs in similar applications.

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Electrical and computer engineering, Electrical engineering
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