Predictive Thread-to-Core Assignment on a Heterogeneous Multi-core Processor

dc.contributor.author Krishnamurthy, Viswanath
dc.contributor.author Sondag, Tyler
dc.contributor.author Rajan, Hridesh
dc.contributor.author Rajan, Hridesh
dc.contributor.department Computer Science
dc.date 2018-02-14T00:00:56.000
dc.date.accessioned 2020-06-30T01:56:11Z
dc.date.available 2020-06-30T01:56:11Z
dc.date.issued 2007-06-29
dc.description.abstract <p>As multi-core processors are becoming common, vendors are starting to explore trade offs between the die size and the number of cores on a die, leading to heterogeneity among cores on a single chip. For efficient utilization of these processors, application threads must be assigned to cores such that the resource needs of a thread closely matches resource availability at the assigned core. Current methods of thread-to-core assignment often require application's execution trace to determine it's runtime properties. These traces are obtained by running the application on some representative input. A problem is that developing these representative input set is time consuming, and requires expertise that the user of a general-purpose processor may not have. In this position paper, we propose an approach for automatic thread-to-core assignment for heterogeneous multi-core processors to address this problem. The key insight behind our approach is simple -- if two phases of a program are similar, then the data obtained by dynamic monitoring of one phase can be used to make scheduling decisions about other similar phases. The technical underpinnings of our approach include: a preliminary static analysis-based approach for determining similarity among program sections, and a thread-to-core assignment algorithm that utilizes the statically generated information as well as execution information obtained from monitoring a small fraction of the program to make scheduling decisions.</p>
dc.identifier archive/lib.dr.iastate.edu/cs_techreports/256/
dc.identifier.articleid 1262
dc.identifier.contextkey 5473792
dc.identifier.s3bucket isulib-bepress-aws-west
dc.identifier.submissionpath cs_techreports/256
dc.identifier.uri https://dr.lib.iastate.edu/handle/20.500.12876/20079
dc.source.bitstream archive/lib.dr.iastate.edu/cs_techreports/256/mainTR.pdf|||Fri Jan 14 22:58:51 UTC 2022
dc.subject.disciplines OS and Networks
dc.subject.disciplines Programming Languages and Compilers
dc.subject.keywords static program analysis
dc.subject.keywords heterogeneous multi-core processors
dc.subject.keywords thread-to-core assignment
dc.subject.keywords phase behavior
dc.title Predictive Thread-to-Core Assignment on a Heterogeneous Multi-core Processor
dc.type article
dc.type.genre article
dspace.entity.type Publication
relation.isAuthorOfPublication 4e3f4631-9a99-4a4d-ab81-491621e94031
relation.isOrgUnitOfPublication f7be4eb9-d1d0-4081-859b-b15cee251456
File
Original bundle
Now showing 1 - 1 of 1
No Thumbnail Available
Name:
mainTR.pdf
Size:
322.05 KB
Format:
Adobe Portable Document Format
Description:
Collections