Techniques for designing robust and reliable analog circuits
Date
2022-12
Authors
Bhatheja, Kushagra
Major Professor
Advisor
Chen, Degang
Huang, Cheng
Neihart, Nathan Mark
Que, Long
Vaswani, Namrata
Committee Member
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Abstract
Recent decades have seen an influx of electronics into high volume safety-critical applications such as automotive. These applications differ from the conventional safety-critical applications like aircrafts in that they operate in a price sensitive market and are available to mass consumers. This makes it difficult to use traditional robustness and reliability mechanisms like redundancy and exhaustive testing. Techniques that can help improve the robustness and reliability of integrated circuits (ICs) to be used in these high-volume safety-critical applications are at the forefront of industrial and academic discussions.
Unlike digital designs, which have managed to achieve very low defects per million, required for the automotive sector, analog designs lag far behind. In fact, analog designs are responsible for the majority of in-field failures observed in any mixed signal system on chip (SoC).
The conventional technique of adding design margins to account for the robustness and reliability is running out of steam. Therefore, techniques such as on-chip functional testing, on-chip transistor degradation monitoring, and lowering AMS test costs in general or through the use of already available on-chip resources is the way forward to deal with these robustness and reliability issues. In this this dissertation all these techniques have been touched upon.
Spectral testing and linearity testing are two primary test categories performed on data converters. On-chip testing of these specifications can help reduce test costs and, improve functional safety through in-field testing. A low cost on-chip sine wave generator for spectral testing has been designed and measurement results obtained in the 40nm bulk CMOS technology.
Taking advantage of the fact that modern SoCs have both ADCs and DACs, an algorithm that can enable co-linearity testing of these data converters without the need for any external equipment has been developed. The algorithm removes the need for requiring a high accuracy signal source or measurement device for the ADC/DAC testing.
A monolithic, fast, large dynamic range gate leakage current monitor has been developed to enable on-chip monitoring/characterization of time dependent dielectric breakdown (TDDB). The developed sensor is sensitive to currents as low as 200pA and directly measures the degrading parameters, that is the gate leakage current unlike previously published designs.
An algorithm to enable high-speed low-cost jitter segregation in pulse amplitude modulation-4 (PAM4) links is also discussed.
Level shifters are an essential component of any modern SoC. Level shifters targeted to charge constraint applications have also been discussed in this thesis.
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Type
dissertation