Analyzing energy savings in an FPGA video processing system using dynamic partial reconfiguration
dc.contributor.advisor | Joseph Zambreno | |
dc.contributor.author | Wernsman, Robert | |
dc.contributor.department | Electrical and Computer Engineering | |
dc.date | 2019-08-21T14:24:55.000 | |
dc.date.accessioned | 2020-06-30T03:16:04Z | |
dc.date.available | 2020-06-30T03:16:04Z | |
dc.date.copyright | Wed May 01 00:00:00 UTC 2019 | |
dc.date.embargo | 2001-01-01 | |
dc.date.issued | 2019-01-01 | |
dc.description.abstract | <p>Dynamic Partial Reconfiguration (DPR) can be a useful tool for maximizing FPGA performance while minimizing power consumption and FPGA size requirements. This work explores the application of the DPR technique in a computer vision application that implements two different edge detection algorithms (FASTX and Sobel). This technique could allow for a similar computer vision system to be realized on a smaller, low-power chipset. Different algorithms can have unique characteristics that yield better performance in certain scenarios; the best algorithm for the current scenario may change during runtime. However, implementing all available algorithms in hardware increases the space and power requirements of the FPGA. We analyze a system that can load an individual edge detection algorithm into the computer vision processing pipeline with negligible interruptions to data processing by using DPR. This application targets the Xilinx UltraScale+ ZCU106 and is able to maintain the same functionality while using an average of 4% less energy when compared to the non-DPR implementation. Additionally, the FPGA utilization for this application is 15% less than that of the traditional implementation that includes both algorithms on the chip at once. These results demonstrate that this technique could allow a similar computer vision system to be realized on a smaller, low-power chipset.</p> | |
dc.format.mimetype | application/pdf | |
dc.identifier | archive/lib.dr.iastate.edu/etd/17122/ | |
dc.identifier.articleid | 8129 | |
dc.identifier.contextkey | 14821691 | |
dc.identifier.s3bucket | isulib-bepress-aws-west | |
dc.identifier.submissionpath | etd/17122 | |
dc.identifier.uri | https://dr.lib.iastate.edu/handle/20.500.12876/31305 | |
dc.language.iso | en | |
dc.source.bitstream | archive/lib.dr.iastate.edu/etd/17122/Wernsman_iastate_0097M_18060.pdf|||Fri Jan 14 21:16:48 UTC 2022 | |
dc.subject.disciplines | Computer Engineering | |
dc.subject.keywords | acceleration | |
dc.subject.keywords | DPR | |
dc.subject.keywords | energy | |
dc.subject.keywords | FPGA | |
dc.subject.keywords | power | |
dc.subject.keywords | video | |
dc.title | Analyzing energy savings in an FPGA video processing system using dynamic partial reconfiguration | |
dc.type | article | |
dc.type.genre | thesis | |
dspace.entity.type | Publication | |
relation.isOrgUnitOfPublication | a75a044c-d11e-44cd-af4f-dab1d83339ff | |
thesis.degree.discipline | Computer Engineering | |
thesis.degree.level | thesis | |
thesis.degree.name | Master of Science |
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