Static and dynamic nonlinearity compensation techniques for high performance current-steering digital-to-analog converters

Abstract

<p>High-speed high-accuracy digital-to-analog converters (DACs) are the crucial building blocks for many signal processing and telecommunication systems. The current-steering architecture is extensively used for these applications. With different decoding schemes--binary-weighted, unary-coded, and segment-coded, current-steering DACs are realized by groups of matched current sources. Their performance is limited by many nonlinear mechanisms such as random mismatch errors, gradient effect, code and voltage dependence of finite output impedance, nonlinear settling time, charge injection, and switch timing errors. In this thesis, two nonlinearity compensation techniques are presented to improve the overall performance of the current-steering DACs.</p> <p>The first design technique is a novel digital calibration technique--complete-folding, which effectively compensates the random mismatch errors by selectively regrouping current sources into a fully binary-weighted array based on current comparisons after chip fabrication. The implementation only requires an analog current comparator and some digital circuitry. The minimum requirement of analog circuits makes complete-folding calibration suitable for DAC design in the low-voltage process. Statistical results with a behavioral model of a 14-bit segmented DAC in MATLAB show that complete-folding calibration can reduce the total gate area of current sources by a factor of almost 1200 compared to the DAC without using any calibration. Additional results also show that this new calibration technique has the superior performance in compensating random mismatch errors as compared to state-of-the-art.</p> <p>The second design technique is a novel output impedance linearization technique that very effectively reduces the code and voltage dependence of finite output impedance. The linearization is achieved by using a small DAC switched with control signals opposite to those for the main DAC. The area and power overhead is less than 5% of the main DAC. Simulation results with a 14-bit segmented current-steering DAC in standard 0.18μm CMOS process show that the DAC's integral nonlinearity (INL) due to finite output impedance is improved by almost 5 bits. Additional results show that this technique is very robust to random mismatch errors. Moreover, not only the static linearity is improved, but most importantly there is a large dynamic linearity enhancement by output impedance linearization. Simulation results show that spurious-free dynamic range (SFDR) can be improved by almost 30 dB at the low signal frequencies and more than 8 dB for the high signal frequencies up to Nyquist rate while sampling at 500MS/s.</p>