A hardware scalable, software configurable LQG controller using a sequential discrete Kalman filter
This thesis details the motivation, architecture, and analysis of a hardware scalable, software programmable Linear Quadratic Gaussian (LQG) controller using a Sequential Discrete Kalman Filter (SDKF) state estimator. While LQG controllers have been around since the 1980s, these controllers have currently not been widely adopted in industry since this algorithm involves a non-trivial matrix inversion. While many accelerated LQG & DKF architectures have been published, these architectures target specific platforms or applications; switching these architecture's application is a non-trivial and time consuming task. Thus, I designed an open-source hardware scalable, software configurable LQG controller, with the intent of others to use this design as an IP core, which will help ease the transition from abstract control theory to practical implementation. The design allows for a user to scale the accelerated LQG hardware architecture while software configurable registers allow the user to configure their controllers without re-synthesizing the hardware design, thus allowing for them to tune their controller on-the-fly. This controller was designed in Xilinx's Vivado 2018.2 design suite, targeting Xilinx ZYNQ series FPGAs, which contain an embedded dual-core ARM Cortex-A9 processor in addition to the traditional FPGA fabric. To compare the performance of this accelerated design, a software implementation of the algorithm was built and tested on three different processor platforms: an embedded ARM Cortex-A9 processor, an AMD FX-9800 series processor, and an Intel i7-4810MQ series processor. For lower dimensional matrices (n = 4), there were modest performance improvements, ranging from 0.79-14.5x improvement for the AMD \& ARM processor, respectively. For larger dimensional matrices (n = 128), the HW/SW LQG achieved a 73x, 102x, and 1390x performance improvement over the Intel, AMD, and ARM processors, respectively. In addition to the software comparison, the analysis is concluded with a comparison of the proposed architecture's size and performance characteristics versus several of the most relevant and recent comparable architectures.