Reese: A method of soft error detection in microprocessors
Date
2000
Authors
Nickel, Joel Bradley
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Somani, Arun K.
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Abstract
In the past, general-purpose processors (GPPs) have been able to increase speed without sacrificing reliable operation. Future processor reliability is threatened by a combination of shrinking transistor size, higher clock rates, reduced supply voltages, and other factors. It is predicted that the occurrence of arbitrary transient faults, or soft errors, will dramatically increase as these trends continue. This thesis proposes and implements a fault-tolerant microprocessor architecture that detects soft errors in its own data pipeline. The goal of this architecture is to accomplish soft error detection without requiring extra program execution time. Similar architectures have been proposed in the past. However, these approaches have not addressed ways of reducing the extra time necessary to implement fault tolerance. The approach in this thesis meets the demands for soft-error detection by using idle capacity that is inherent in the microprocessor pipeline. In our approach, every instruction is executed twice. The first execution is the primary execution, and the second is the redundant execution. After both are done, the two results are compared, and soft errors can be detected. Our approach, called REESE (REdundant Execution using Spare Elements), improves on past methods and, when necessary, adds a minimal amount of hardware to the processor. We add hardware only to minimize the increased execution time due to the redundant instructions.
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thesis