Configuration cache management systems for striped FPGAs
Date
2000
Authors
Sarosh, Zulfiqar Hussain
Major Professor
Advisor
Somani, Arun K.
Committee Member
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Abstract
The striped FPGA is designed to map pipelined applications onto given hardware. The stripes are configured to carry out the operation of individual stages in a pipelined application. The configuration data is stored in an on-chip cache. The cache may not be large enough to hold all the configurations required for an application. A scheme to manage the on-chip cache is required. In this paper five such schemes are studied. The All in Cache (AiC) scheme assumes that all configurations can be loaded in the cache. The cache replacement schemes manage the cache by de-allocating space from selected configurations to load new configurations. Two such schemes are proposed in this paper. In the Most Recently used (MRU) scheme any configuration, other than the k most recently used configuration, may be removed randomly. In the Most Frequently used (MFU) scheme the configurations with highest frequency of use in the application reside in the cache. The rest of the configurations are loaded from the off-chip device as needed. The configuration generation schemes are based on the assumption that similar configurations may be generated from some base configuration with the help of a modifier. In the Base and Modifier in Cache (BMC) scheme all the base configurations and configuration modifiers are in the cache. The Base in Cache (BiC) scheme stores only the base configuration in the cache. The modifiers are loaded at the run time. The results of our simulations indicate that if all configurations required by an application cannot fit in the cache then BMC and BiC give better performance. These schemes out perform even the AiC, if the number of base configurations and data elements is small.
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