Dual-frequency dual-inductor multiple-outputs (DF-DIMO) buck converter topologies with fully-integrated output filters

dc.contributor.advisor Ayman Fayed
dc.contributor.author Jiang, Yongjie
dc.contributor.department Electrical and Computer Engineering
dc.date 2018-08-11T11:17:58.000
dc.date.accessioned 2020-06-30T03:00:43Z
dc.date.available 2020-06-30T03:00:43Z
dc.date.copyright Fri Jan 01 00:00:00 UTC 2016
dc.date.embargo 2017-04-21
dc.date.issued 2016-01-01
dc.description.abstract <p>In multi-core DSPs, there is a need for multiple independent power supplies to power the digital cores. Each power supply needs to have fast dynamic response and must support a wide range of output voltage with up to hundreds of mA load current. In this dissertation, the key performance metrics in power converter design are introduced, the advantages and dis-advantages of the conventional power converter topology are analyzed and a new Dual-Frequency Dual-Inductor Multiple-Output (DF-DIMO) buck converter topology is presented to improve the limitations of the conventional topologies. The proposed topology employs a dual-phase 20-MHz current-mode-controlled input stage to reduce the inductance required per phase to only 200 nH, and a 4-output 100-MHz comparator-controlled fully-integrated output stage to reduce the capacitance required per output to 10 nF. To enable each output to handle up to 250-mA load with less than 40-mV voltage ripple, a 3rd-order bond-wire-based notch filter is employed at each output for voltage ripple suppression. Additionally, the proposed design employs dynamic output re-ordering to enhance dynamic and cross-regulation performance, interleaved pulse-skipping to enhance light-load efficiency, and high-gain local output feedback to enhance DC load Regulation. Targeting multi-core DSPs, the proposed design is implemented in standard 65-nm CMOS technology with 1.8-V input, and outputs in the range of 0.6–1.2 V with a total load of 1 A. It achieves a peak efficiency of 74%, less than 40-mV output voltage ripple, 0.5-V/70-ns Dynamic Voltage Scaling (DVS), and settling time of less than 85 ns for 125-mA all with no cross regulations.</p>
dc.format.mimetype application/pdf
dc.identifier archive/lib.dr.iastate.edu/etd/15000/
dc.identifier.articleid 6007
dc.identifier.contextkey 8881001
dc.identifier.doi https://doi.org/10.31274/etd-180810-4605
dc.identifier.s3bucket isulib-bepress-aws-west
dc.identifier.submissionpath etd/15000
dc.identifier.uri https://dr.lib.iastate.edu/handle/20.500.12876/29184
dc.language.iso en
dc.source.bitstream archive/lib.dr.iastate.edu/etd/15000/Jiang_iastate_0097E_15601.pdf|||Fri Jan 14 20:34:26 UTC 2022
dc.subject.disciplines Electrical and Electronics
dc.subject.keywords Electrical Engineering
dc.subject.keywords Dynamic Voltage Scaling
dc.subject.keywords High-Frequency Inductor-based Power Converters
dc.subject.keywords Integrated DC-DC Power Converters
dc.subject.keywords Power Management
dc.subject.keywords SIMO Power Converters
dc.title Dual-frequency dual-inductor multiple-outputs (DF-DIMO) buck converter topologies with fully-integrated output filters
dc.type article
dc.type.genre dissertation
dspace.entity.type Publication
relation.isOrgUnitOfPublication a75a044c-d11e-44cd-af4f-dab1d83339ff
thesis.degree.discipline Electrical Engineering
thesis.degree.level dissertation
thesis.degree.name Doctor of Philosophy
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