Dynamic branch decoupled architecture
Date
1998
Authors
Ng, Hon-Chi
Major Professor
Advisor
Mohapatra, Prasant
Tyagi, Akhilesh
Committee Member
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Abstract
Branch instructions in pipelined processors introduce control hazards that stall the pipeline until the branch outcomes are resolved. Memory latency adds additional penalty for taken branches. With typical branch frequency of about 20%, impact of branches on processor performance is quite significant. In this thesis, a dynamic branch decoupled architecture is proposed to determine the outcome of branches early in order to eliminate the control hazards. A branch decoupled processor contains two processing units, namely program processing unit and branch processing unit. The instructions fetched are checked for dependence and decoupled into two streams, namely branch stream and program stream, where branch stream contains instructions that lead to branch outcomes (branch-determining instructions) and program stream contains all instructions except branch instructions. They are concurrently executed by the corresponding processing units.
The branch outcomes are expected to be resolved early by the branch processing unit, so that the program processing unit can execute without stalling its pipeline. Such instruction decoupling is performed dynamically, so that dynamic branch decoupled processor is compatible at object-level for the existing executable binaries without requiring re-compilation. Branch predictions are commonly used in contemporary processors as solutions to the control hazards. A 2-level adaptive branch predictor typically achieves 90% accuracy, however, there is still 10% probability of mis-prediction. Simulations show that a dynamic branch decoupled processor has a performance gain of up-to 40% over 2-level adaptive branch predictor for integer benchmarks.
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thesis