A high speed 8-tap digital adaptive equalizer design

Abstract

The advent of the information age brings an enormous growing demand for the storage of digital data in magnetic disks. The density of data stored in a single magnetic disk has had to increase to accommodate this growing demand. Adaptive equalization as an efficient signal processing technique can be used in magnetic disk read channels to increase the storage density. Adaptive equalizer is the signal processing system realizing the adaptive equalization. The demand for increasing storage density and accessing speed keeps pushing the adaptive equalizer for increasing speed. Digital adaptive equalizer has the potential to achieve high speed while retains high performance. The particular focus of this research is the design of a 6-bit input, 8-tap digital adaptive equalizer IC in HP 0.5[mu]m process with application in magnetic disk read channels.

The sample rate of the equalizer may reach up to 400MHz (at 25 0C). In this adaptive equalizer design, Sign-Error Least Mean Square algorithm (SE-LMS) is used for coefficient updating. This research covers IC structure design, submodule design, circuit design, floorplanning and layout with emphasis on the transistor level design and optimization. In this thesis, a 6bx6b lookup table based pipelined multiplier is proposed, which not only has high speed but also has low latency. A high-speed adder structure is also proposed. This type of adder is used in the multiplier and the summing chain. Furthermore, by use of this adder structure, an accumulator with saturation logic, which is used for coefficient update, is designed. In the thesis, the background in related area is first reviewed. A number of design issues are discussed in the order of the design procedure. At the end of the thesis, simulation results are presented, the summary is given and possible future work is suggested.