No inclusion in multi level caches Vasudevan, Bharath
dc.contributor.department Electrical and Computer Engineering 2020-08-05T05:04:54.000 2021-02-26T08:45:03Z 2021-02-26T08:45:03Z Wed Jan 01 00:00:00 UTC 2003 2003-01-01
dc.description.abstract <p>Inclusive property in multi-level cache has been the norm in most processor architectures. Nevertheless, recent trends in cache implementations call for a reexamination of this issue. This thesis analyzes and evaluates the traditional inclusive scheme, no-inclusiON scheme and mutual exclusion scheme. Using a Simple Scalar-based simulation and the SPEC2000 benchmark, it is been shown that the no-inclusion scheme, one of the non-inclusion schemes, provides the best performance. Further the thesis proposes two techniques to optimize the no inclusion scheme by selectively writing back data from L1 to L2. The first optimization filters out stack data that are unlikely to be accessed again immediately, and the second one filters out non-stack data of poor temporal locality. The two techniques not only reduce the L1-L2 traffic but also improve the efficiency of L2 cache as a backup storage. The simulation results show that these optimizations may reduce the main memory accesses by up to 23% and improve the performance of the no-inclusion scheme by up to 9%.</p>
dc.format.mimetype application/pdf
dc.identifier archive/
dc.identifier.articleid 21070
dc.identifier.contextkey 18791867
dc.identifier.s3bucket isulib-bepress-aws-west
dc.identifier.submissionpath rtd/20071
dc.language.iso en
dc.source.bitstream archive/|||Fri Jan 14 22:19:26 UTC 2022
dc.subject.keywords Electrical and computer engineering
dc.subject.keywords Computer engineering
dc.title No inclusion in multi level caches
dc.type article
dc.type.genre thesis
dspace.entity.type Publication
relation.isOrgUnitOfPublication a75a044c-d11e-44cd-af4f-dab1d83339ff Computer Engineering thesis Master of Science
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