Optimizing message-passing performance within symmetric multiprocessor systems

dc.contributor.author Chen, Xuehua
dc.contributor.department Electrical and Computer Engineering
dc.date 2020-08-05T18:36:37.000
dc.date.accessioned 2021-02-26T08:41:19Z
dc.date.available 2021-02-26T08:41:19Z
dc.date.copyright Wed Jan 01 00:00:00 UTC 2003
dc.date.issued 2003-01-01
dc.description.abstract <p>The Message Passing Interface (MPI) has been widely used in the area of parallel computing due to its portability, scalability, and ease of use. Message passing within Symmetric Multiprocessor (SMP) systems is an import part of any MPI library since it enables parallel programs to run efficiently on SMP systems, or clusters of SMP systems when combined with other ways of communication such as TCP/IP. Most message-passing implementations use a shared memory pool as an intermediate buffer to hold messages, some lock mechanisms to protect the pool, and some synchronization mechanism for coordinating the processes. However, the performance varies significantly depending on how these are implemented. The work here implements two SMP message-passing modules using lock-based and lock-free approaches for MPLi̲te, a compact library that implements a subset of the most commonly used MPI functions. Various optimization techniques have been used to optimize the performance. These two modules are evaluated using a communication performance analysis tool called NetPIPE, and compared with the implementations of other MPI libraries such as MPICH, MPICH2, LAM/MPI and MPI/PRO. Performance tools such as PAPI and VTune are used to gather some runtime information at the hardware level. This information together with some cache theory and the hardware configuration is used to explain various performance phenomena. Tests using a real application have shown the performance of the different implementations in real practice. These results all show that the improvements of the new techniques over existing implementations.</p>
dc.format.mimetype application/pdf
dc.identifier archive/lib.dr.iastate.edu/rtd/19929/
dc.identifier.articleid 20928
dc.identifier.contextkey 18780027
dc.identifier.doi https://doi.org/10.31274/rtd-20200803-151
dc.identifier.s3bucket isulib-bepress-aws-west
dc.identifier.submissionpath rtd/19929
dc.identifier.uri https://dr.lib.iastate.edu/handle/20.500.12876/97296
dc.language.iso en
dc.source.bitstream archive/lib.dr.iastate.edu/rtd/19929/Chen_ISU_2003_C546.pdf|||Fri Jan 14 22:01:15 UTC 2022
dc.subject.keywords Electrical and computer engineering
dc.subject.keywords Computer engineering
dc.title Optimizing message-passing performance within symmetric multiprocessor systems
dc.type article
dc.type.genre thesis
dspace.entity.type Publication
relation.isOrgUnitOfPublication a75a044c-d11e-44cd-af4f-dab1d83339ff
thesis.degree.discipline Computer Engineering
thesis.degree.level thesis
thesis.degree.name Master of Science
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