Preventing integrated circuit piracy using reconfigurable logic barriers

dc.contributor.advisor Joseph Zambreno
dc.contributor.advisor Akhilesh Tyagi
dc.contributor.author Baumgarten, Alex
dc.contributor.department Electrical and Computer Engineering
dc.date 2018-08-11T05:41:57.000
dc.date.accessioned 2020-06-30T02:31:01Z
dc.date.available 2020-06-30T02:31:01Z
dc.date.copyright Thu Jan 01 00:00:00 UTC 2009
dc.date.embargo 2013-06-05
dc.date.issued 2009-01-01
dc.description.abstract <p>With each new feature size, integrated circuit (IC) manufacturing costs increase. Rising expenses cause the once vertical IC supply chain to flatten out. Companies are increasing their reliance on contractors, often foreign, to supplement their supply chain deficiencies as they no longer can provide all of the services themselves. This shift has brought with it several security concerns classified under three categories: (1) Metering - controlling the number of ICs created and for whom. (2) Theft - controlling the dissemination of intellectual property (IP). (3) Trust - controlling the confidence in the IC post-fabrication. Our research focuses on providing a solution to the metering problem by restricting an attacker's access to the IC design. Our solution modifies the CAD tool flow in order to identify locations in the circuit which can be protected with reconfigurable logic barriers. These barriers require the correct key to be present for information to flow through. Incorrect key values render the IC useless as the flow of information is blocked. Our selection heuristics utilize observability and controllability don't care sets along with a node's location in the network to maximize an attacker's burden while keeping in mind the associated overhead. We implement our approach in an open-source logic synthesis tool, compare it against previous solutions and evaluate its effectiveness against a knowledgeable attacker.</p>
dc.format.mimetype application/pdf
dc.identifier archive/lib.dr.iastate.edu/etd/10790/
dc.identifier.articleid 1787
dc.identifier.contextkey 2806985
dc.identifier.doi https://doi.org/10.31274/etd-180810-363
dc.identifier.s3bucket isulib-bepress-aws-west
dc.identifier.submissionpath etd/10790
dc.identifier.uri https://dr.lib.iastate.edu/handle/20.500.12876/24996
dc.language.iso en
dc.source.bitstream archive/lib.dr.iastate.edu/etd/10790/Baumgarten_iastate_0097M_10639.pdf|||Fri Jan 14 18:27:58 UTC 2022
dc.subject.disciplines Electrical and Computer Engineering
dc.subject.keywords Fabrication
dc.subject.keywords Integrated Circuit
dc.subject.keywords Piracy
dc.subject.keywords Reconfigurable
dc.subject.keywords Security
dc.subject.keywords VLSI
dc.title Preventing integrated circuit piracy using reconfigurable logic barriers
dc.type article
dc.type.genre thesis
dspace.entity.type Publication
relation.isOrgUnitOfPublication a75a044c-d11e-44cd-af4f-dab1d83339ff
thesis.degree.level thesis
thesis.degree.name Master of Science
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