Simultaneous placement and timing optimization using buffer insertion, cell replication and gate sizing

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Nowak_ISU_2001_N69.pdf (2.82 MB)
Date
2001-01-01
Authors
Nowak, Brian
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Altmetrics
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Electrical and Computer Engineering
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https://doi.org/10.31274/rtd-20210128-78
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https://dr.lib.iastate.edu/handle/20.500.12876/98829
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