Design techniques for ultra low voltage CMOS continuous-time filters and continuous-time sigma-delta modulators

dc.contributor.advisor Edward K. F. Lee
dc.contributor.author Huang, Huanzhang
dc.contributor.department Electrical and Computer Engineering
dc.date 2018-08-25T01:48:01.000
dc.date.accessioned 2020-06-30T07:05:00Z
dc.date.available 2020-06-30T07:05:00Z
dc.date.copyright Mon Jan 01 00:00:00 UTC 2001
dc.date.issued 2001-01-01
dc.description.abstract <p>In recent years, the increasing market and the increasing need of battery-operated portable equipment have pushed the industry to put much more efforts on developing new circuit techniques and new circuit structures to design circuit that can operate at very low supply voltages and with reduced power dissipation. Reducing power supply is a natural solution to reduce power consumption. However, reducing power supply does not always mean almost the same performance and low power consumption. All of the above facts have produced the urgent necessity to find new circuit design techniques that can produce circuits operating at power supply voltage in the range of 1V to 2V.;In this dissertation, a technique that can be used to design low voltage CMOS continuous-time analog circuits is proposed. Some biasing current sources are added to the inverting or non-inverting opamp terminals such that the opamp input common-mode voltages could be shifted close to one of the supply rails for allowing low voltage operations.;A digital frequency and Q tuning technique is proposed for low-voltage active RC filters that uses programmable capacitor arrays (PCAs). The proposed technique does not require any peak detectors, which are difficult to implement at low-voltage.;A direct digital background tuning technique for the notch frequency of continuous-time sigma-delta modulator is proposed to solve the large SNR loss problem caused by the deviation of the actual notch frequency from the desired value due to process and temperature changes.;To demonstrate the proposed low voltage design technique, the frequency and Q tuning technique, and the notch frequency tuning technique, a 1V continuous-time filter and a 1.2V continuous-time band pass sigma-delta modulator prototypes are designed, fabricated and tested. For a 5 kHz sine wave input signal, the filter achieves a THD of -60.2 dB for a peak-to-peak output voltage of 600 mV. The measured power consumption for the filter alone consumes about 0.52mW for a supply voltage of +/-0.5V. The measured DR for the 1.2V modulator is about 40dB(6.5bit) and the peak SNR is 44dB(7bit). The power consumption is 2.1mW.</p>
dc.format.mimetype application/pdf
dc.identifier archive/lib.dr.iastate.edu/rtd/1046/
dc.identifier.articleid 2045
dc.identifier.contextkey 6090396
dc.identifier.doi https://doi.org/10.31274/rtd-180813-13138
dc.identifier.s3bucket isulib-bepress-aws-west
dc.identifier.submissionpath rtd/1046
dc.identifier.uri https://dr.lib.iastate.edu/handle/20.500.12876/63608
dc.language.iso en
dc.source.bitstream archive/lib.dr.iastate.edu/rtd/1046/r_3016711.pdf|||Fri Jan 14 18:21:20 UTC 2022
dc.subject.disciplines Electrical and Electronics
dc.subject.disciplines Oil, Gas, and Energy
dc.subject.keywords Electrical and computer engineering
dc.subject.keywords Electrical engineering (Microelectronics)
dc.subject.keywords Microelectronics
dc.title Design techniques for ultra low voltage CMOS continuous-time filters and continuous-time sigma-delta modulators
dc.type article
dc.type.genre dissertation
dspace.entity.type Publication
relation.isOrgUnitOfPublication a75a044c-d11e-44cd-af4f-dab1d83339ff
thesis.degree.level dissertation
thesis.degree.name Doctor of Philosophy
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