Partitioned cache shadowing for deep sub-micron (DSM) regime

Date
2005-01-01
Authors
Xu, Heng
Somani, Arun
Somani, Arun
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Electrical and Computer Engineering
Abstract

An important issue in modern cache designs is bridging the gap between wire and device delays. This warrants the use of more regular and modular structures to mask wire latencies. This paper advances the basic concepts of shadow caching to offer protection against both data corruption and micro-network disruption in partitioned architectures. Network disruption is tolerated by sending shadow packet along a different route than the original packet, whereas the data corruption problem is addressed by reserving a small portion of the overall cache capacity for in-cache shadow space. Our results show that an average of 96% in data error coverage for Spec2K benchmarks can be achieved and more than 99% of the transient faults on the underlying switched micro-network can also be protected while incurring less than 3% performance degradation in most of the above benchmarks.

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This is a manuscript of a proceeding published as Xu, Heng, and Arun Somani. "Partitioned cache shadowing for deep sub-micron (DSM) regime." In 11th Pacific Rim International Symposium on Dependable Computing (PRDC'05) (2005): 8. DOI: 10.1109/PRDC.2005.48. Posted with permission.

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