Switched capacitor, self referencing sensing scheme for high density magneto-resistive memories

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Ranmuthu, Indumini
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Chester S. Comstock
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Electrical and Computer Engineering

The Department of Electrical and Computer Engineering (ECpE) contains two focuses. The focus on Electrical Engineering teaches students in the fields of control systems, electromagnetics and non-destructive evaluation, microelectronics, electric power & energy systems, and the like. The Computer Engineering focus teaches in the fields of software systems, embedded systems, networking, information security, computer architecture, etc.

The Department of Electrical Engineering was formed in 1909 from the division of the Department of Physics and Electrical Engineering. In 1985 its name changed to Department of Electrical Engineering and Computer Engineering. In 1995 it became the Department of Electrical and Computer Engineering.

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  • Department of Electrical Engineering (1909-1985)
  • Department of Electrical Engineering and Computer Engineering (1985-1995)

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Magneto-resistive elements have possible applications in memories and sensors. Recently considerable effort has been directed towards the development of high density magneto-resistive memories. This research includes work in many areas such as obtaining cells with higher signal levels, densification of storage cells and the development of an appropriate sensing scheme. This dissertation deals with the development of latter stages of a multi stage sensing scheme for a large magneto-resistive memory. In this sensing scheme the signal of a actual element is compared against the signal from a dummy element. The resulting signal is stored and again is compared against a signal of opposite polarity which is generated from the same element. This process is called self referencing and is done to minimize offset problems. The special features of this sensing scheme are: the balanced sensing where the signal from the actual and the dummy elements are balanced to have identical time constants, a two stage switched capacitor auto-zero scheme where the DC offsets between the two elements due to mismatch is removed while generating very little noise and self referencing which is done by a sample and compare circuit. This self referencing process increases the bit density by 50% and the two stage auto-zero significantly reduces read access time. The memory is nonvolatile, radiation hard and is designed to have a read access time of 800ns.

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Fri Jan 01 00:00:00 UTC 1993