Accurate Jitter Decomposition in High-Speed Links

dc.contributor.advisor Degang Chen
dc.contributor.author Duan, Yan
dc.contributor.department Electrical and Computer Engineering
dc.date 2018-08-11T22:38:59.000
dc.date.accessioned 2020-06-30T03:09:57Z
dc.date.available 2020-06-30T03:09:57Z
dc.date.copyright Sun Jan 01 00:00:00 UTC 2017
dc.date.embargo 2018-04-20
dc.date.issued 2017-01-01
dc.description.abstract <p>In a high-speed digital communication system, jitter performance plays a crucial role in Bit-Error Rate (BER). It is important to accurately derive each type of jitter as well as total jitter (TJ) and to identify the root causes of jitter by jitter decomposition.</p> <p>In this work, we propose new jitter decomposition techniques in high-speed links testing. The background of jitter decomposition is described in chapter 1. In chapter 2, duty cycle distortion jitter amplification is introduced. As channel loss results in both ISI and jitter amplification, DCD amplification is a big concern in high-speed links. The derivation of a formula of DCD amplification for data channels is included and the calculation result matches the time-domain simulation in the system.</p> <p>Chapter 3 provides an accurate jitter decomposition algorithm using Least Squares (LS) which simultaneously separates ISI, RJ, and PJ. A new time domain ISI model is proposed, which is faster and more accurate than the conventional ISI model. This algorithm obtains the estimated individual jitter component value with fine accuracy by using less samples of total jitter data compared with conventional methods. The simulation and measurement show the accuracy and efficiency of this algorithm with less data samples.</p> <p>In chapter 4, a low-cost comparator-based jitter decomposition algorithm is proposed. Instead of using TIE jitter sequence to decompose, it uses a low cost and simple comparator network to identify the deviation of current sampling positions from the ideal sampling positions to represent the TIE. It simultaneously separates ISI, DCD, and PJ and can achieve similar accuracy compared to the instrument test. Both the simulation and measurement show the decomposition algorithm with great accuracy and efficiency.</p> <p>In chapter 5, a low cost and simple dithering method to improve the test of linearity of analog-to-digital converter (ADC) is proposed. This method exhibits an improvement and enhancement for the ultra-fast segmented model identification of linearity error (uSMILE) algorithm which reduces 99% of the test time compared to the conventional method. In this study, we proposed three types of distribution dithering methods adding to the ramp input signal to reduce the estimation error when uSMILE was applied in low resolution ADCs. The fix pattern distribution was proved as the most efficient and cost-effective method by comparing with the Gaussian, uniform, and fix-pattern distributions. Both the simulation results and hardware measurement indicate that the estimation error can be significantly reduced in 12-bit SAR ADC with effective dithering.</p>
dc.format.mimetype application/pdf
dc.identifier archive/lib.dr.iastate.edu/etd/16276/
dc.identifier.articleid 7283
dc.identifier.contextkey 12307519
dc.identifier.doi https://doi.org/10.31274/etd-180810-5907
dc.identifier.s3bucket isulib-bepress-aws-west
dc.identifier.submissionpath etd/16276
dc.identifier.uri https://dr.lib.iastate.edu/handle/20.500.12876/30459
dc.language.iso en
dc.source.bitstream archive/lib.dr.iastate.edu/etd/16276/Duan_iastate_0097E_16542.pdf|||Fri Jan 14 20:57:32 UTC 2022
dc.subject.disciplines Electrical and Electronics
dc.title Accurate Jitter Decomposition in High-Speed Links
dc.type article
dc.type.genre dissertation
dspace.entity.type Publication
relation.isOrgUnitOfPublication a75a044c-d11e-44cd-af4f-dab1d83339ff
thesis.degree.discipline Electrical Engineering
thesis.degree.level dissertation
thesis.degree.name Doctor of Philosophy
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