Feasibility study of silicon pixel detector

Date
2002-01-01
Authors
Tanadi, Trismardawi
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Altmetrics
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Electrical and Computer Engineering
Abstract

Ancient Greek philosophers believed that atom was the smallest part of matter and was indivisible. In the time since, scientists have continually accumulated information that shows the inconsistency of the idea of the atom as the smallest particle. Modern physicists have shown the existence of subatomic particles. As part of the effort to help answer questions about the nature of the subatomic particles, the Relativistic Heavy Ion Collider (RHIC) was built at Brookhaven National Laboratory. RHIC is a complex piece of machinery whose primary function is to smash high-speed ions into each other, hopefully creating a shower of subatomic particles in the collision. In order to detect the resulting particles, many different types of detectors have been proposed and employed. Monolithic silicon pixel detectors have been studied extensively because we can have the detecting element and the readout electronics integrated onto the same silicon wafer. Couple advantages of this approach compare to having separate silicon wafers for the detecting element and the readout electronic are: (1) Thin device. (2) No detector-electronic connection. We are able to improve the speed of the MIMOSA chip of LEPSI/IreS by employing column in parallel readout instead of serial readout. We also propose a new pixel structure that would give us the ability for the array to sample the events at the same time. A new read out technique of Read-Read-Again is also being implemented. The idea of this technique is basically read each particular pixel twice, once for the actual signal excited by particle hit and then we reset the pixel before we read the second time for the reset signal. The Read-Read-Again technique will compensate the fixed pattern noise (FPN) for the non-uniformity of the threshold voltage of the source follower transistor in the pixel. Our study shows that monolithic silicon pixel detector is feasible to be built in the custom twin-tub CMOS fabrication process. This is good because a well-established fabrication process already exists. Our study also shows a promising result of employing the Read-Read-Again technique.

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