Power conversion techniques in nanometer CMOS for low-power applications

dc.contributor.advisor Ayman Fayed
dc.contributor.author Fu, Wei
dc.contributor.department Electrical and Computer Engineering
dc.date 2018-08-11T15:11:37.000
dc.date.accessioned 2020-06-30T02:55:48Z
dc.date.available 2020-06-30T02:55:48Z
dc.date.copyright Thu Jan 01 00:00:00 UTC 2015
dc.date.embargo 2017-04-18
dc.date.issued 2015-01-01
dc.description.abstract <p>As System-on-Chip (SoCs) in nanometer CMOS technologies grow larger, the power management process within these SoCs becomes very challenging. In the heart of this process lies the challenge of implementing energy-efficient and cost-effective DC-DC power converters. To address this challenge, this thesis studies in details three different aspects of DC-DC power converters and proposes potential solutions. First, to maximize power conversion efficiency, loss mechanisms must be studied and quantified. For that purpose, we provide comprehensive analysis and modeling of the various switching and conduction losses in low-power synchronous DC-DC buck converters in both Continuous Conduction Mode (CCM) and Discontinuous Conduction Mode (DCM) operation, including the case with non-rail gate control of the power switches. Second, a DC-DC buck converter design with only on-chip passives is proposed and implemented in 65-nm CMOS technology. The converter switches at 588 MHz and uses a 20-nH and 300-pF on-chip inductor and capacitor respectively, and provides up to 30-mA of load at an output voltage in the range of 0.8-1.2 V. The proposed design features over 10% improvement in power conversion efficiency over a corresponding linear regulator while preserving low-cost implementation. Finally, a 40-mA buck converter design operating in the inherently-stable DCM mode for the entire load range is presented. It employs a Pulse Frequency Modulation (PFM) scheme using a Hysteretic-Assisted Adaptive Minimum On-Time (HA-AMOT) controller to automatically adapt to a wide range of operating scenarios while minimizing inductor peak current. As a result, compact silicon area, low quiescent current, high efficiency, and robust performance across all conditions can be achieved without any calibration.</p>
dc.format.mimetype application/pdf
dc.identifier archive/lib.dr.iastate.edu/etd/14307/
dc.identifier.articleid 5314
dc.identifier.contextkey 7896932
dc.identifier.doi https://doi.org/10.31274/etd-180810-3861
dc.identifier.s3bucket isulib-bepress-aws-west
dc.identifier.submissionpath etd/14307
dc.identifier.uri https://dr.lib.iastate.edu/handle/20.500.12876/28492
dc.language.iso en
dc.source.bitstream archive/lib.dr.iastate.edu/etd/14307/Fu_iastate_0097E_14831.pdf|||Fri Jan 14 20:18:15 UTC 2022
dc.subject.disciplines Electrical and Electronics
dc.subject.keywords Electrical Engineering
dc.subject.keywords circuit and system
dc.subject.keywords nanometer CMOS
dc.subject.keywords power converter
dc.subject.keywords VLSI
dc.title Power conversion techniques in nanometer CMOS for low-power applications
dc.type article
dc.type.genre dissertation
dspace.entity.type Publication
relation.isOrgUnitOfPublication a75a044c-d11e-44cd-af4f-dab1d83339ff
thesis.degree.level dissertation
thesis.degree.name Doctor of Philosophy
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