A new programmable low noise all digital phase-locked loop architecture

dc.contributor.author Gaither, Justin
dc.date 2019-03-12T09:38:59.000
dc.date.accessioned 2020-06-30T08:10:18Z
dc.date.available 2020-06-30T08:10:18Z
dc.date.copyright Sat Jan 01 00:00:00 UTC 2005
dc.date.issued 2005-01-01
dc.description.abstract <p>In the electronics industry today almost without exception there are phase-locked loops (PLL) implemented within each system and often within each integrated circuit (IC). In fact, most PLL's are implemented monolithically within ICs without any or with very few external components. Additionally, most are implemented as Analog PLL's utilizing only a digital phase detector. This is also evident in the majority of recent publications which focus on PLL structures with on-chip voltage controlled oscillators using charge pumps and ring or LC oscillators. However, the problem with most on-chip VCO's is that they are far noisier than the external crystal types. The noise in the integrated oscillators forces designers to use larger loop bandwidths than would be required with less noisy VCO's; subsequently they have poor noise filtering capabilities. Additionally, analog PLL's are usually fixed in nature. Loop components such as charge-pumps and loop filters are implemented as analog components with little or no flexibility. The focus of this thesis is the design and implementation of a very low cost, low noise Programmable All Digital PLL (ADPLL) which utilizes a low cost digital to analog converter (DAC), a voltage controlled crystal oscillator (VCXO), and a field programmable gate array (FPGA). The use of FPGA technology for digital design implementation is universal in the industry and provides benefits far beyond the implementation of ADPLL's. In fact, in almost every system today, an FPGA already exists. Therefore, the inclusion of a DPLL within existing system components would be at little or no cost. The implementation of the PLL digitally not only allows us to implement it within an FPGA, but also allows us to adapt and configure the PLL for many applications and tune it for best performance. Digital circuits also have increased noise margin and are not affected by the same noise issues associated with Analog PLL's such as temperature, voltage and noise coupled from other signals or circuits. The DPLL developed is flexible and can be configured to operate as a clock and data recovery circuit (CDR), clock multiplier, clock synthesizer, or noise filtering PLL. Using an external VCXO provides a very low noise basis for the PLL and such that we can implement very low bandwidths without sacrificing the quality of its output. In this thesis we will present the theory, architecture, design, hardware and implementation of the ADPLL in addition to the results of the testing of the prototype ADPLL that was built.</p>
dc.format.mimetype application/pdf
dc.identifier archive/lib.dr.iastate.edu/rtd/18752/
dc.identifier.articleid 19752
dc.identifier.contextkey 13860810
dc.identifier.s3bucket isulib-bepress-aws-west
dc.identifier.submissionpath rtd/18752
dc.identifier.uri https://dr.lib.iastate.edu/handle/20.500.12876/72686
dc.language.iso en
dc.source.bitstream archive/lib.dr.iastate.edu/rtd/18752/Gaither_ISU_2005_G35.pdf|||Fri Jan 14 21:46:14 UTC 2022
dc.subject.keywords Computer Engineering
dc.title A new programmable low noise all digital phase-locked loop architecture
dc.type article
dc.type.genre thesis
dspace.entity.type Publication
thesis.degree.discipline Computer Engineering
thesis.degree.level thesis
thesis.degree.name Master of Science
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