On-Chip Adaptive Circuits for Fast Media Processing

Date
2006-09-01
Authors
Sangireddy, Rama
Somani, Arun
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Abstract

Applications, depending on their nature, demand either higher computing capacity, larger data-storage capacity, or both. Hence, providing on-chip memory and computing resources that are fixed in nature is expensive and does not enable an efficient utilization of on-chip silicon real estate. In this brief, we design the circuit of an adaptive register file computing (ARC) unit, a novel on-chip dual-role circuit with a minimal area overhead of 0.233 mm 2 at 0.18-mu technology. It supplements the conventional register bank to provide larger register storage capacity or acts as a specialized computing unit to provide higher on-chip computing capacity, depending on the requirement of a specific application. The brief discusses the circuit-level details for the implementation of the dual-role ARC unit, its integration in a wide-issue processor pipeline, and the corresponding performance enhancement in various multimedia applications.

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This is a manuscript of an article published as Sangireddy, Rama, and Arun K. Somani. "On-chip adaptive circuits for fast media processing." IEEE Transactions on Circuits and Systems II: Express Briefs 53, no. 9 (2006): 946-950. DOI: 10.1109/TCSII.2006.880336. Posted with permission.

Keywords
Multimedia, reconfigurable computing, register file
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